A Regulator Design for a SerDes PHY of a High Speed Serial Data Interface
نویسنده
چکیده
—A fully integrated 3.3 V-to-1.2 V supply voltage regulator for application in IEEE 1394B PHY has been designed in 0.13μm SMIC Mixed Signal process technology. The regulator is able to deliver peak current transient of 300 mA, while the output voltage remain within a margin of 10% around the nominal value. The PSRR response larger than 52 dB for frequencies up to 10 kHz under the condition of IL=300 mA. The FOM of the circuit can be better than 2.5. The circuit can be used in all types of high speed serial data communication system.
منابع مشابه
Design and Implementation of a High Speed Systolic Serial Multiplier and Squarer for Long Unsigned Integer Using VHDL
A systolic serial multiplier for unsigned numbers is presented which operates without zero words inserted between successive data words, outputs the full product and has only one clock cycle latency. 
The multiplier is based on a modified serial/parallel scheme with two adjacent multiplier cells. Systolic concept is a well-known means of intensive computational task through replication of fu...
متن کاملDesign and Implementation of a High Speed Systolic Serial Multiplier and Squarer for Long Unsigned Integer Using VHDL
A systolic serial multiplier for unsigned numbers is presented which operates without zero words inserted between successive data words, outputs the full product and has only one clock cycle latency. The multiplier is based on a modified serial/parallel scheme with two adjacent multiplier cells. Systolic concept is a well-known means of intensive computational task through replication of func...
متن کاملAn Intelligent Computer Interface Utilizing Parallel Picocontrollers (TECHNICAL NOTE)
The design of an interface unit is described, in which RS232 serial data is converted to latched parallel data on 22 independent lines. The data direction of each line is programmable through the serial port. Two picocontrollers are employed in a parallel processing mode to give the required number of I/O pins, and data on the shared serial line is coded to separate data streams to the individu...
متن کاملEvaluate Serializer-Deserializer (SerDes) Performance by Creating Eye Pattern Templates - AN4099
Maxim has developed a family of serializer and deserializer products for high-speed, serial data interconnection in video display and digital image sensing. Today's designers are very interested in the performance measurement and margin of a serial data link established by a serializer and deserializer (SerDes) chipset. This application note presents an experimental approach first to measure th...
متن کاملDesign of a 6.25 Gbps Backplane SerDes with TOP-down Design Methodology
SerDes design exceeding 6.25 Gbps for existing backplanes has to overcome significant signal integrity challenges on channel attenuation, cross talk, and multiple reflections. Adaptive decision feedback equalization becomes a requirement to overcome these challenges. The non-ideality from silicon implementation is not negligible for bit error rate degradation. This paper presents a 6.25 Gbps ba...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
- JCM
دوره 9 شماره
صفحات -
تاریخ انتشار 2014